Shift binops appear to mutate their right operand.

3028619
Opened by Roy Frostig at 2010-08-26 23:29:43

The following program:

fn main() {
  let uint b = 1u;
  while (b <= 32u) {
    0u << b;
    b <<= 1u;
    log b;
  }
}

Gives the following output:

rt: 8d08:main:main:                       rust: 2 (0x2)
rt: 8d08:main:main:                       rust: 8 (0x8)
rt: 8d08:main:main:                       rust: 2048 (0x800)

The shift-left 0u << b is necessary to make this happen, but 0u >> b and 0u >>> b suffice to reproduce the bug just as well. Also, changing b <<= 1u to b = b << 1u makes the bug go away.

  1. Make vreg constrs per-quad, regfence on nontrivial constrs, back out workaround to _uint, add regression test. Closed by 7cfa7bdd23c1fed92a5e52f33437fbaeec4c235b.

    Graydon Hoare at 2010-08-26 23:29:43